This application claims the priority of Korean Patent Application No. 2003-95399, filed on Dec. 23, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a transconductor circuit, and more particularly, to a transconductor circuit including metal oxide semiconductor (MOS) transistors so as to prevent an output current from being distorted.
2. Description of the Related Art
In general, transconductors are circuits that convert a voltage into a current to process an electric signal. In other words, when a predetermined voltage is applied to the transconductors, the transconductors output a current value. Such a transconductor is generally used in an analog signal processor such as a filter, a gain variable amplifier, or the like.
The transconductor is processed by a highly integrated analog signal and includes MOS or complementary MOS (CMOS) transistors that are generally driven at a low voltage. The MOS transistors have merits in that an input gate current does not flow, power consumption is low, and integration is high.
FIG. 1 is a circuit diagram of a conventional transconductor circuit. Referring to FIG. 1, a transconductor circuit 10 includes an input unit 20, an output unit 30, and current sources 40.
The input unit 20 is a differential pair and includes first and second MOS transistors M1 and M2 and a resistor R1. First and second input voltages Vinn and Vinp are applied to gates of the first and second MOS transistors M1 and M2, respectively. A source of the first MOS transistor M1 is electrically connected to a source of the second MOS transistor M2 via the resistor R1. Here, the input unit 20 serves as a main circuitry of the transconductor circuit 10. Since the input unit 20 is the differential pair and includes a pair of the first and second MOS transistors M1 and M2 as above-mentioned, the input unit 20 is advantageous to operation speed characteristics. Here, an output current is less distorted when the resistor R1 exists than when the resistor R1 does not exist.
The output unit 30 is a cascode amplifier in which gates of third and fourth MOS transistors M3 and M4 are commonly connected. A source of the third MOS transistor M3 is connected to a drain of the first MOS transistor M1, and a source of the fourth MOS transistor M4 is connected to a drain of the second MOS transistor M2. Predetermined electric loads (not shown) are connected to drains of the third and fourth MOS transistors M3 and M4 so as to allow the output current to flow through the transconductor circuit 10. A power voltage Vdc is applied to gates of the third and fourth MOS transistors M3 and M4.
The current sources 40 are respectively connected between the first MOS transistor M1 and ground and between the second MOS transistor M2 and ground to supply the first and second MOS transistors M1 and M2 with constant bias.
It preferable that a gate-source voltage Vgs of the first and second MOS transistors M1 and M2 is low and transconductances gm of the first and second MOS transistors M1 and M2 are high in order to drive the transconductor circuit 10 at a low voltage. Also, it is preferable that gate-drain capacitances Cgd of the first and second MOS transistors M1 and M2 are low to improve fast operation characteristics. Moreover, the first and second MOS transistors M1 and M2 are preferably designed so that channel lengths are short and ratios of channel widths to channel lengths are great.
A transconductance Gm of the transconductor circuit 10 is a variation in the output current with respect to an input voltage and can be represented as in Equation:
                    Gm        =                              ⅆ                          (              Iout              )                                            ⅆ                          (              Vin              )                                                          (        1        )            wherein Iout denotes the output current that is a difference (Iop-Ion) between a second current Iop and a first current Ion, and Vin denotes the input voltage that is a difference (Vinp-Vinn) between the second input voltage Vinp and the first input voltage Vinn.
In the transconductor circuit 10, the first and second input voltages Vinn and Vinp applied to the first and second MOS transistors M1 and M2 of the input unit 20 vary the first and second currents Ion and Iop. Here, the output unit 30 is connected to an output node of the input unit 20 to increase entire output resistance in the transconductor circuit 10.
The transconductance Gm of the transconductor circuit 10 must be constant regardless of the intensity of the input voltage Vin. However, as shown in FIG. 2, the transconductance Gm of the transconductor circuit 10 gradually decreases when an absolute value of the input voltage Vin increases to a constant voltage or more. This means that the output current lout of the transconductor circuit 10 is distorted.
The distortion of the output current Iout is generally caused by the nonlinear characteristics of the first and second MOS transistors M1 and M2 resulting from a power voltage and a bias current value generated from the power voltage. The distortion of the output current lout may be considerably reduced by increasing the magnitude of the resistor R1 of the input unit 20.
However, the increase in the magnitude of the resistor R1 results in increasing the size of semiconductor chips and parasitic capacitance, which deteriorates integration density and operation speed.
Although the magnitude of the resistor R1 increases, the nonlinear characteristics of the first and second MOS transistors M1 and M2 and the current sources 40 do not vary. Also, as shown in FIG. 2, as the input voltage Vin of the transconductor circuit 10 gets close to a maximum input voltage Vmax, the distortion of the output current lout becomes more serious. Furthermore, when the output current lout is distorted, a region in which the output current lout linearly increases is reduced.